1. Field of the Invention
The invention relates to an image signal processing method and device, and more particularly to an image signal processing method and device for a LCD (liquid crystal display) monitor.
2. Description of the Related Art
The cathode ray tube (CRT) display technology is always the mainstream of display for a long time, and its associated technology is well developed after several tens of years of improvements. Recently, the display technology has been greatly modified owing to the trend of digitalization. Thus, the digital display tends to replace the CRT monitor.
Unlike the operation method of the conventional analog display, the digital signals of the digital display replace the electron beams of the CRT monitor. So, the digital display may be made thinner and lighter, and makes it possible to get rid of the problems of radiation and frame flickers. The liquid crystal display (LCD) and the plasma display panel (PDP) is representative of the mainstreams of the present digital display technology. At present, because the LCD technology is suitable for the small-scale display and the domestic televisions are mainly the CRT monitors, the application field of the LCD technology in the market is wider than that of the PDP technology.
In the applications of the personal computers, because the display cards (VGA cards) of many computer systems can only output analog image signals, the LCD has to convert the analog signals into digital signals for display. Therefore, the image processing device of the LCD must have an analog front end (AFE) device and a scalar for performing operations of signal conversion and scaling, wherein the AFE device is for converting analog image signals into digital image signals, while the scalar is for computing the digital image signals so as to obtain images with various resolutions.
The function of the AFE device is to convert analog image signals, which are composed of three primary colors of red (R), green (G), and blue (B), into digital image signals. A typical AFE device has three sets of ADCs (analog-to-digital converters) 110, 130 and 150 for converting red analog signals RA, green analog signals GA and blue analog signals BA into red digital signals RD, green digital signals GD and blue digital signals BD, respectively, as shown in FIG. 1. In the AFE device, the most important portion is the high-speed ADC, the performance of which directly influences the frame quality of the LCD monitor. Taking a 15″ LCD monitor as an example, if the display mode is 1024×768×85 Hz (XGA mode), the ADC has to work at 94.500 MHz. That is, the clock generator 170 has to output clock signals CLK with 94.500 MHz to the ADCs 110, 130 and 150. With the development of the LCD technology, there will be more and more large-scale panels to be commercialized. If a 17″ LCD monitor is operating under the SXGA mode (1280×1024×85 Hz), the working clock of the ADC may reach 157.500 MHz. Consequently, an ADC with high-speed and medium resolution plays an important role in the AFE device. With the increasing of the integration degree of the chip, the current trend is to integrate the AFE device, the scalar and other peripheral circuits on the same chip, which is called as a LCD control chip.
The required clock of the ADC will get higher and higher as the resolution of the liquid crystal panel gets higher and higher. However, owing to the support limitation of the manufacturing process, it is difficult to implement the ADC having a working clock higher than a certain extreme value. In order to overcome such a problem, the interleaved circuit architecture having increased speed but large area is adopted during the design phase. In such methods, an ADC working at the frequency f may be equivalent to an odd converter and an even converter both working at the frequency f/2, and the analog signals are converted into an odd signal and an even signal. Thereafter, a selector (e.g., a multiplexer) working at the frequency f is adopted to alternatively output the odd signal and the even signal, both of which may be combined into the desired digital signal. FIG. 2 is a schematic illustration showing an interleaved ADC. Taking the conversion of the red analog signal RA as an example, the odd converter 211 and the even converter 213 of the ADC 210 operate, according to the clock signal HCLK, to convert the red analog signal RA into a red odd signal RDO and a red even signal RDE, respectively. Thus, the frequency of each of the red odd signal RDO and the red even signal RDE is the same as that of the clock signal HCLK. The multiplexer 220 alternatively switches between the odd converter 211 and the even converter 213 according to the clock signal CLK, and the red odd signal RDO and the red even signal RDE may be combined into the red digital signal RD for output accordingly. The frequency of the clock signal CLK is twice that of the clock signal HCLK and may be implemented by the frequency divider 270. Similarly, the odd converter 231 and the even converter 233 of the ADC 230 may convert the green analog signal GA into the green odd signal GDO and the green even signal GDE, both of which are then combined into the green digital signal GD by the multiplexer 240. The odd converter 251 and the even converter 253 of the ADC 250 may convert the blue analog signal BA into the blue odd signal BDO and the blue even signal BDE, both of which are then combined into the blue digital signal BD by the multiplexer 260.
Simply speaking, in the interleaved architecture, the analog signals of the three primary colors may be converted into the digital signals with the frequency f if each ADC works at the frequency f/2. Consequently, the circuit design difficulty may be greatly reduced, but a larger circuit area is required.
FIG. 3 shows timing charts of the clock signals CLK and HCLK, the red odd signal RDO, the red even signal RDE and the red digital signal RD, wherein the frequency of the clock signal CLK is one half that of the clock signal HCLK. As mentioned above, the frequency of each of the red odd signal RDO and the red even signal RDE is the same as that of the clock signal HCLK. The multiplexer alternatively switches between the odd converter and the even converter according to the clock signal CLK so as to combine the red odd signal RDO and the red even signal RDE into the red digital signal RD, wherein the frequency of the red digital signal RD is the same as that of the clock signal CLK. Similarly, the methods for forming the green and blue digital signals are also the same as that for forming the red digital signal, and detailed descriptions thereof will be omitted.
In the high-frequency mode, digital signals of the three primary colors are combined by the odd and even signals generated from the odd and even converters, respectively. Therefore, if the odd and even converters have unsymmetrical circuit architectures caused by the differences of manufacturing processes or other reasons, fine ripples with different brightness will be caused in the gray-scale frame. FIG. 4 is a schematic illustration showing the actual gray-scale distribution of the digital signal. It is assumed that the odd symbols denote the pixels (e.g., pixels P1, P3, P5, . . . P11 ) for the odd signals outputted from the odd converters, and the even symbols denote the pixels (e.g., pixels P2, P4, P6, . . . P12) for the even signals outputted from the even converters. Theoretically, each pixel value should fall on the horizontal line, as shown in FIG. 4A. However, because the circuit architectures of the odd and even converters are not symmetrical, the pixel value is not the same as the theoretical value. In some cases (e.g., in this embodiment), it is possible that all pixel values corresponding to the odd signals outputted from the odd converters are higher than the theoretical values, and all pixel values corresponding to the even signals outputted from the even converters are lower than the theoretical values (or the odd pixel values are lower and the even pixel values are higher, depending on the circuit designs). Consequently, interleaved fine ripples with different brightness in the gray-scale frame will be produced. Of course, it is inevitably that the odd or even signals are different from the theoretical values. That is, one of the odd or even signals may coincide with the theoretical values). However, in terms of outputting the same pixel value, the odd signal will be indispensably different from the even signal, which is the main reason causing the different brightness.
Of course, such a problem directly influences the image quality. The influence will become more significant in the display mode of lower frequency or the frame with the simpler background, and will be found by the user. Hence, it is necessary to find and solve the source of the problem in order to improve the display effect of the monitor and to enhance the display quality.